1. Technical Field
The present invention relates to a semiconductor device including plural transistors having different gate lengths.
2. Related Art
There is a conventional semiconductor device as disclosed in, for example, Japanese Laid-open patent publication NO. 2004-356520. FIG. 9 illustrates a semiconductor device described in the same literature. The semiconductor device 100 includes a first transistor 110 and a second transistor 112 on a semiconductor substrate 105. The first transistor 110 includes a first gate electrode portion 116 constituted by a first gate insulating film 124 and a first gate electrode 126 which are stacked in this order. The second transistor 112 includes a second gate electrode portion 120 constituted by a second gate insulating film 132 and a second gate electrode 130 which are stacked in this order. A device isolation layer 114 is formed in the semiconductor substrate 105 between the first transistor 110 and the second transistor 112. The first transistor 110 and the second transistor 112 respectively include a pair of impurity diffusion layers 118 and 122 formed at the surface layer of the semiconductor substrate 105. Side walls 128 and 134 are formed on the sidewalls of the first and second gate electrodes 126 and 130, respectively.
FIGS. 10A and 10B illustrate schematic cross-sectional views of the first gate electrode portion 126 and the second gate electrode portion 130. Further, the side walls 128 and 134 are not illustrated therein. In the semiconductor device 100, the grain size of the poly-silicon grains 136 forming the first gate electrode 126 is adjusted to be greater than the grain size of the poly-silicon grains 138 forming the second gate electrode 130. The first gate electrode 126 and the second gate electrode 130 are formed by diffusing impurities into the grain boundaries of the poly-silicon grains.